1. Field of the Invention
The present invention relates to a MOS transistor and a manufacturing method thereof, and more specifically, to a MOS transistor and a manufacturing method thereof, in which a modified silicon channel is formed using silicon carbide, thereby improving a drive current of the MOS transistor, and in which a nickel salicide layer may be formed using silicon carbide so that the MOS transistor has low resistance contact characteristics.
2. Background of the Related Art
With the rapid development of high-speed and high-integration semiconductor devices, micro-sized transistors have been realized. As the semiconductor devices have become highly integrated, a drive current of the semiconductor device may be reduced, so that the performance of the semiconductor device may be degraded. In order to solve this problem, various methods have been suggested. One of them is a method of improving mobility of carriers by applying the stress to silicon.
Conventionally, a strained silicon (strained-Si) epitaxial layer is formed by using a silicon germanium (SiGe) epitaxial layer in order to apply the stress to silicon. However, such a silicon epitaxial layer may cause lattice damage to silicon, thereby increasing leakage current of the MOS transistor.
Another conventional method is to induce a vertically isotropic tension stress by depositing a nitride layer on a gate and a spacer after forming a strained-Si epitaxial layer using a SiGe epitaxial layer. However, this method may increase the manufacturing cost due to the addition of a nitride layer depositing process.
Meanwhile, a contact for a metal wiring must be formed after a gate electrode and a source-drain active region of a semiconductor device have been formed, in order to electrically connect the gate electrode and the source-drain active region to external devices. However, surface resistance of the thin polycrystalline silicon gate and the source-drain active region, which are prepared corresponding to the scale-down of the semiconductor device, generally are not reduced to a level below a range between 10 to 20 ohms/square. For this reason, utility of the thin polycrystalline silicon gate and the source-drain active region, which serve as interconnection media, may be significantly reduced.
In order to solve the above problem by improving the interconnection characteristics of the thin polycrystalline silicon gate and the source-drain active region, a salicide layer having a low specific resistance is formed on the gate and silicon of the source-drain active region. In this case, parasitic capacitance derived from overlap of the source-drain and the gate can be reduced and a contact area between a metal wiring and the source-drain may increase, so that the contact resistance and internal resistance of the source-drain can be reduced.
Among conventional salicide forming processes, a nickel salicide process forms a nickel salicide (e.g., Ni2Si) layer by reacting silicon of the source-drain region with nickel. However, the nickel salicide layer obtained through the above nickel salicide process is generally thermally unstable at a temperature of 500° C. or above, which corresponds to the temperature of a chemical vapor deposition process for forming a subsequent (e.g., inter-metal) layer, which may cause contact leakage current. To solve this problem, there has been suggested a method of implanting nitrogen (N) or Ni—Pt ions into nickel. However, this method introduces an additional manufacturing cost.